This invention relates to pulse monitoring systems and in particular to systems for detecting the pulse width of received signals.
Transmitted digital signals need their pulse widths to remain within a prescribed tolerance in order for the receiving circuitry to be able to ascertain the data content of the transmitted signals. A transmitted digital signal may become distorted by frequency response effects of the transmitting medium, by loss of energy over distance, electromagnetic interference, etc.
With reference to FIG. 1, two sample pulse sequences are shown. Both begin with a logic low and transition to a logic high. In the case of a logic low, TLmin denotes the minimum allowed pulse length of a logic low pulse and TLmax denotes the maximum allowed pulse length for a logic low pulse. In order for a receiving circuit to accept a logic low to high transition, the incoming pulse low signal should transition within a window of time defined by the difference of TLmax and TLmin. This window of time is defined as logic low transition window, W0, in FIG. 1. Similarly, a logic high pulse also needs to have a pulse length defined by a minimum logic high pulse length, THmin, and a maximum logic high pulse length, THmax. In order for a logic high to low transition to be accepted, the transition should occur within a window of time defined by the difference of THmax and THmin. This window of time is defined as a logic high transition window, W1. As shown with the two sample pulse sequences of FIG. 1, the time windows W0 and W1 need not be the same for different applications, although they typically should remain constant within a single application.
The receiving circuit includes a pulse detecting sub-circuit to observe the pulse length of received pulse signals. Prior art pulse detecting circuit typically observe only one of the logic high or logic low pulse of a received signal, but not both. This means that the pulse detecting circuit cannot determine the signal period of the received pulse signal, and thus cannot observe shifts in the signal""s frequency. Frequency shifts in a received pulse signal can therefore lead to undetected errors.
Prior art pulse detecting circuits typically use two one-shot circuits to determine if a received signal is valid for a predetermined transition window. Both one-shot circuits are typically triggered on the leading edge of an received pulse signal. A first one-shot circuit issues a first pulse having a length equal to the minimum pulse length requirement, and the second one-shot circuit issues a second pulse having a length equal to the maximum pulse length requirement. At the end of the second pulse, the received signal is compared with the first and second pulse. If the length of the received pulse does not lie within the first and second pulse, then no detection signal is issued and the received pulse signal is ignored. One shot-circuits, however, are difficult to control or adjust in integrated circuitry. Additionally, they do not provide for a simple way of adjusting the required transition window for different applications.
This prior art approach can also slow down a system since the pulse detecting circuit waits for the lapse of the maximum pulse length before verifying the received pulse signal. In effect, it waits the maximum amount of delay time for each received pulse signal even if the received pulse signal transition earlier and do not require any additional wait time. U.S. Pat. No. 3,735,271 to Leibowitz shows a pulse width detecting circuit that does not wait for the maximum allowable pulse length before testing for a valid received pulse signal. The ""271 circuit, however, requires three one-shot circuits and adds a delay to each received pulse signal. This added delay may actually cause additional errors. Assuming the circuit receives a pulse signal having a pulse length slightly shorter than the minimum require pulse length, the added pulse delay introduced by ""271 may actually cause the circuit to think that the received signal did meet the minimum pulse length requirement.
It is an object of the present invention to provide a pulse detecting circuit that observes both a received pulse signal""s pulse length and its frequency.
It is another object of the present invention to provide a pulse detecting circuit that observes both logic high and logic low pulse of a received pulse signal.
It is yet another object of the present invention to provide a pulse detecting circuit that lends itself to simple integration onto an IC circuit and that permits its allowable pulse transition windows W0 and W1 to be independently, or jointly, adjusted from inside and from outside the IC circuit.
The above objects are met in a pulse detection circuit that uses a pair of linear voltage ramp generators and a reference voltage source for establishing a preferred pulse length window for a received pulse signal. The present pulse detection circuit monitors both the positive duty cycle and the negative duty cycle of a received pulse signal. Therefore, it can detect frequency shifts in the received pulse signals. If a positive or negative duty cycle is found to be either too short or too long, it is categorized a xe2x80x9cbadxe2x80x9d duty cycle and an error signal is issued that disables the internal circuitry of a chip. If the duty cycle lies within a predetermined time window, i.e. a preferred pulse transition window, it is categorized as a xe2x80x9cgoodxe2x80x9d duty cycle. If an error signal is issued due to encountering a bad duty cycle, the internal circuitry of the chip remains disabled until two consecutive good duty cycles are observed. When the present pulse detection circuit receives two consecutive good pulses, i.e. good high pulse following a good low pulse, or a good low pulse following a good high pulse, it issues an enable signal to re-enable the internal circuitry of the chip.
The present duty cycle monitoring circuit includes two monitoring sub-circuits. A first sub-circuit monitors the positive duty cycle of an incoming pulse signal, and a second sub-circuit monitors the negative duty cycle of the incoming pulse signal. Since the positive and negative duty cycles are monitored by separate sub-circuits, the present pulse detection circuit can support different preferred pulse transition windows for positive duty cycles and for negative duty cycles. For the sake of brevity, only the first sub-circuit for monitoring a positive duty cycle described here. The circuit structure for the second sub-circuit is similar to the first sub-circuit and is discussed in detail in the best mode description below.
A preferred pulse transition window, W1, for a xe2x80x9cgoodxe2x80x9d positive duty cycle is first defined. This pulse transition window is established by means of a slower linear voltage ramp and a faster linear voltage ramp working in unison. As time passes, the voltage difference between the slower and faster linear voltage ramps increases, and this voltage difference becomes a measure of the a duty cycle duration. A desired duration window is established by noting the voltage value of the slower linear voltage ramp when the voltage difference between the slower and faster linear voltage ramps becomes representative of the desired pulse transition window. This noted voltage value becomes a reference voltage to which an incoming clock is compared. In other words, the length of a pulse transition window can be adjusted or shifted in time by changing the reference voltage or by adjusting the slope of the linear voltage ramp generators. The reference voltage may be generated from within the circuit or may be supplied from a source external to the circuit.
As logic state of an incoming clock changes from low to high, the slower and faster voltage ramps are reset and re-triggered. A first comparator is used to compare the rising voltage value of the faster voltage ramp with the reference voltage. The first comparator signals when the faster voltage ramp rises above the reference voltage. A second comparator is used to compare the rising voltage value of the slower voltage ramp with the same reference voltage. The second comparator signals when the slower ramp rises above the reference voltage. The received pulse signal is within the desired pulse length while only while the faster voltage ramp is above the reference voltage and the slower voltage ramp is below the reference voltage. If either comparator indicates that these conditions are not true, then the duty cycle of the incoming clock is outside the desired window and it is categorized as a xe2x80x9cbadxe2x80x9d duty cycle.
Upon the trailing edge of the received pulse, the output of the comparators is analyzed and the result stored in a first register. A second register stores the result of the previous received pulse. The state, good or bad, of the current pulse is compared with the state, good or bad, of the previous pulse. If the state the current pulse is bad, then a disable signal is issued. If the state of the current pulse is good, but the state of the previous pulse is bad, then the disable signal remains issued. If the state of the current pulse and the previous pulse are both good, then an enable signal is issued.
Additionally, included is an initiation circuit that maintains a constant disable signal during the first few received pulse signals at start-up. This gives the internal circuitry time to achieve a known state before being enabled by the pulse detecting circuit.